A 1T Dynamic Random Access Memory Cell Based on Gated Thyristor with Surrounding Gate Structure for High Scalability.

Area of Science:

• Solid State Physics
• Semiconductor Device Physics
• Materials Science

Background:

• Conventional one-transistor (1T) dynamic random access memory (DRAM) cells often rely on the floating body effect, which can limit performance.
• The need for scalable and high-speed memory solutions is critical for advancing computing technologies.

Purpose of the Study:

• To investigate a novel 1T DRAM cell architecture based on a gated-thyristor device.
• To evaluate the potential of voltage-driven bistability for achieving high-speed DRAM operations.
• To assess the scalability and operational characteristics of the proposed gated-thyristor DRAM cell.

Main Methods:

• Device simulation using a commercial simulator to analyze operational mechanisms.
• Characterization of current-voltage (I-V) properties and bias dependence.
• Evaluation of DRAM operation principles within the proposed cell structure.

Main Results:

• The proposed gated-thyristor DRAM cell utilizes voltage-driven bistability, avoiding excess carrier generation seen in conventional cells.
• Carrier injection from the n+ cathode region enables high-speed operation capabilities.
• The sidewall gate structure facilitates high scalability for array integration.

Conclusions:

• The novel gated-thyristor 1T DRAM cell demonstrates significant advantages in terms of high-speed operation.
• The device architecture offers superior scalability for constructing dense memory arrays.
• This technology presents a promising alternative for next-generation DRAM applications.