A 1T Dynamic Random Access Memory Cell Based on Gated Thyristor with Surrounding Gate Structure for High Scalability

In this study, we investigate a one-transistor (1T) dynamic random access memory (DRAM) cell based on a gated-thyristor device utilizing voltage-driven bistability to enable high-speed operations. The structural feature of the surrounding gate using a sidewall provides high scalability with regard to constructing an array architecture of the proposed devices. In addition, the operation mechanism, I-V characteristics, DRAM operations, and bias dependence are analyzed using a commercial device simulator. Unlike conventional 1T DRAM cells utilizing the floating body effect, excess carriers which are required to be stored to make two different states are not generated but injected from the n+ cathode region, giving the device high-speed operation capabilities. The findings here indicate that the proposed DRAM cell offers distinct advantages in terms of scalability and high-speed operations.