An 18-ps TDC using timing adjustment and bin realignment methods in a Cyclone-IV FPGA.

Area of Science:

• Digital electronics
• Integrated circuit design
• Signal processing

Background:

• Field-programmable gate arrays (FPGAs) are widely used for implementing digital systems.
• Time-to-digital converters (TDCs) are crucial components for precise timing measurements.
• Traditional tapped delay line (TDL) methods in FPGAs face challenges in achieving optimal time resolution.

Purpose of the Study:

• To implement a high-precision time-to-digital converter (TDC) on an Altera Cyclone-IV FPGA.
• To enhance time interpolation accuracy using a tapped delay line (TDL) architecture.
• To improve the differential nonlinearity and time resolution of the FPGA-based TDC.

Main Methods:

• Implemented a TDC utilizing a tapped delay line (TDL) on an Altera Cyclone-IV FPGA.
• Applied timing adjustment to tune carry look-up table (LUT) cell delays via low-level primitives.
• Performed bin realignment based on timing adjustment results to ensure a uniform TDL.

Main Results:

• Achieved a root-mean-square (RMS) timing resolution of 18 ps.
• Obtained a least-significant bit (LSB) resolution of 45 ps.
• Demonstrated improved differential nonlinearity and time resolution through bin realignment.

Conclusions:

• The proposed timing adjustment and bin realignment method effectively enhances TDC performance on FPGAs.
• The implemented FPGA TDC offers high precision suitable for demanding timing applications.
• This technique provides a viable approach for optimizing TDL-based TDCs in FPGA designs.