High-Performance All-Printed Amorphous Oxide FETs and Logics with Electronically Compatible Electrode/Channel...

Area of Science:

• Materials Science
• Electronics Engineering
• Semiconductor Physics

Background:

• Oxide semiconductors offer superior performance over amorphous silicon and organic materials, particularly when deposited via physical vapor deposition.
• Reproducing consistent device characteristics in solution-processed/printed oxide field-effect transistors (FETs), especially with integrated passive elements, presents significant challenges.
• Developing printable electronic components requires precise control over the electrode/channel interface for optimal performance.

Purpose of the Study:

• To develop a protocol for designing electronically compatible electrode/channel interfaces for printed oxide FETs.
• To demonstrate high-performance all-printed FETs and logic circuits using amorphous indium-gallium-zinc oxide (a-IGZO) and indium tin oxide (ITO).
• To investigate the interfacial effects influencing the electrical performance of printed oxide semiconductor devices.

Main Methods:

• Judicious selection of electrode and channel materials to create an optimized interface.
• Fabrication of all-printed FETs and logic circuits utilizing amorphous indium-gallium-zinc oxide (a-IGZO) semiconductor, indium tin oxide (ITO) electrodes, and a composite solid polymer electrolyte gate insulator.
• Compressive spectroscopic studies to analyze the band alignment and doping effects at the a-IGZO/ITO interface.

Main Results:

• Achieved high-performance all-printed FETs with optimal threshold voltages and device mobility, comparable to devices with sputtered ITO electrodes.
• Identified the formation of an In-Sn-Zn-O (ITZO)-based-diffused a-IGZO-ITO interface, crucial for controlling doping density and ensuring high electrical performance.
• Spectroscopic analysis confirmed that Sn doping-mediated band alignment between a-IGZO and ITO electrodes is key to the observed excellent device performance.
• Successfully demonstrated all-printed n-MOS-based logic circuits, paving the way for next-generation portable electronics.

Conclusions:

• The developed protocol enables the fabrication of high-performance all-printed oxide FETs and logic circuits.
• The strategic selection of electrode/channel materials from the same oxide family creates a beneficial diffused interface for enhanced device characteristics.
• This work provides a pathway for advanced, low-cost, and large-area printed electronics for various applications.