ASIC Implementation of a Nonlinear Dynamical Model for Hippocampal Prosthesis.

Area of Science:

• Neuroscience
• Biomedical Engineering
• Integrated Circuit Design

Background:

• Cognitive dysfunction necessitates advanced neural prosthetics.
• Hippocampal prostheses require efficient, implantable biochips for brain integration.
• Existing very large scale integration (VLSI) biochips face limitations in power and area.

Purpose of the Study:

• To propose a novel, low-complexity, small-area, and low-power application-specific integrated circuit (ASIC) for a hippocampal prosthesis.
• To implement a programmable hippocampal neural network based on the multi-input, multi-output (MIMO)-generalized Laguerre-Volterra model (GLVM).
• To achieve real-time prediction of hippocampal neural activity using the developed ASIC.

Main Methods:

• Design of a novel hardware architecture for the hippocampal neural network ASIC.
• Implementation of a storage space configuration scheme and low-power convolution modules.
• Integration of a Gaussian random number generator and fabrication using 40 nm technology.

Main Results:

• The ASIC achieved a core area of 0.122 mm² and a test power of 84.4 µW.
• Compared to traditional architectures, the core area was reduced by 84.94%.
• The core power consumption was reduced by 24.30%.

Conclusions:

• The proposed ASIC offers a significant reduction in area and power consumption for hippocampal prostheses.
• The novel design enables efficient, real-time prediction of hippocampal neural activity.
• This development advances the feasibility of sophisticated neural implants for cognitive dysfunction.