The Micro-Analysis Estimation of 3D FinFET ICs in High Temperature Operation

An integrated circuit failure mode in inter metal layer dielectric micro-delamination of the advanced 16 nm FinFET process in high temperature operating test was investigated and presented by micro-analysis firstly in the paper. With the smaller size in metal level and device level, the joule heat and temperature effect inversion (TEI) become the significant concerned point in the new technology node. Through high temperature operation test, it's verified in the commercial system-on-chip product combined application processor function. With series of experimental result and failure analysis, a high temperature caused functional fail was demonstrated. The localized joule heat was generated from IC operating current which induced by the voltage and temperature. High temperature and voltage overstress induced the ICs higher joule heat generated locally which is a new reliability concern in advanced process layout plan and the power consideration by circuit design view. For FinFET IC's working conditions (ex: environmental temperature) and application (ex: high processor usage or high performance), the whole chip design should be well simulated and estimated before entering mass production stage. The failure characteristic in this study provides a hint to reconsider the factor of localized heating in the advanced process system-on-chip circuit design and layout shrinkage in application.