A 0.18-μm CMOS high-data-rate true random bit generator through ΔΣ modulation of chaotic jerk circuit signals

A full-custom design of chaos-based True Random-Bit Generator (TRBG) implemented on a 0.18-μm CMOS technology is presented with unique composition of three major components, i.e., (i) chaotic jerk oscillator, (ii) ΔΣ modulator, and (iii) simple pre/post-processing. A chaotic jerk oscillator is a deterministic source of randomness that potentially offers robust and highly random chaotic signals and exhibits a distinctive property of smoothly balanced-to-unbalanced alternation of double-scroll attractors. The continuous-time 2nd-order ΔΣ modulator is introduced as a mixed-signal interface in order to increase a resolution of random bit sequences while no extra clock is required. The ΔΣ modulator is constructed mainly by a folded-cascode amplifier with sufficient gain and phase margin of 64 dB and 83°, respectively, and a high-speed comparator with a time constant of 2.7 ns. An uncomplicated structure of shift-registers is realized as a post-processing process. The bit sequence of the proposed TRBG successfully passes all statistical tests of NIST SP800-22 test suite, and the ultimate output bit rate is 50 Mbps. The physical layout of a chip area is 212.8 × 177.11 μm and the DC power dissipation is 1.32mW using a 1.8-V single supply voltage. This paper therefore offers a potential alternative to a fully embedded cryptographic module in ASIC applications.