A Speed- and Power-Efficient SPIHT Design for Wearable Quality-On-Demand ECG Applications.

Area of Science:

• Digital Signal Processing
• Biomedical Engineering
• Integrated Circuit Design

Background:

• Existing Set Partitioning in Hierarchical Trees (SPIHT) algorithms for electrocardiography (ECG) compression suffer from low coding speeds and complex hardware architectures.
• Wearable quality-on-demand (QoD) ECG applications require real-time, low-power compression solutions.
• One-dimensional (1-D) discrete wavelet transform (DWT) is crucial for ECG signal processing.

Purpose of the Study:

• To develop a speed and power-efficient SPIHT design for 1-D wavelet-based ECG compression systems.
• To achieve real-time performance and low power consumption for wearable QoD ECG applications.
• To guarantee quality during ECG data compression.

Main Methods:

• Proposed a coding-time- and computation-efficient SPIHT algorithm utilizing coding status register files.
• Developed a highly pipelined and power-efficient Very Large Scale Integration (VLSI) architecture for SPIHT implementation.
• Validated the design using 11-level 1024x1-D DWT on MIT-BIH arrhythmia datasets with varying Percentage Root-Mean-Square Difference (PRD) targets.

Main Results:

• The proposed SPIHT algorithm achieved 1.52 to 2.74 times faster average coding time compared to prior methods at identical compression ratios.
• The VLSI architecture achieved a working frequency of 740 MHz and consumed an average of 23 μW using 90-nm CMOS technology.
• Demonstrated significant improvements in speed and power efficiency over state-of-the-art designs.

Conclusions:

• The developed SPIHT algorithm and VLSI architecture effectively address the speed and power efficiency challenges in wavelet-based ECG compression.
• The design is suitable for real-time, low-power wearable QoD ECG applications.
• The proposed solution offers a significant advancement for portable and efficient biomedical signal processing.