Runtime Programmable and Memory Bandwidth Optimized FPGA-Based Coprocessor for Deep Convolutional Neural Network.

Area of Science:

• Computer Engineering
• Artificial Intelligence
• Hardware Acceleration

Background:

• Deep convolutional neural networks (DCNNs) require significant computational power and memory bandwidth, posing challenges for power-constrained environments.
• General-purpose CPUs are inefficient for DCNN computations due to their inability to exploit inherent parallelisms.

Purpose of the Study:

• To propose and evaluate a field-programmable gate array (FPGA)-based runtime programmable coprocessor for accelerating DCNN feed-forward computations.
• To design a coprocessor that offers flexibility for new network architectures without hardware resynthesis, acting as a plug-and-use peripheral.

Main Methods:

• Implemented a runtime programmable coprocessor on a Xilinx Virtex-7 FPGA.
• Utilized on-chip memory for caching input features and filter weights to reduce external memory bandwidth.
• Incorporated data prefetching and optimization techniques for efficient data reuse and dynamic dataflow adjustment.

Main Results:

• Achieved consistent computational throughput exceeding 140 G operations/s across various input and filter sizes.
• Demonstrated superior energy efficiency compared to highly optimized CPU implementations.
• Significantly reduced off-chip memory transactions through effective on-chip caching.

Conclusions:

• The FPGA-based coprocessor provides an energy-efficient and high-throughput solution for accelerating DCNNs.
• Runtime programmability and efficient memory management enable adaptability to diverse DCNN architectures.
• This approach addresses the computational demands of DCNNs in power-constrained applications.