Chip-Scale Coils for Millimeter-Sized Bio-Implants.

Area of Science:

• Biomedical Engineering
• Microsystems Engineering
• Neurotechnology

Background:

• Next-generation implantable neural interfaces require mm-scale, wireless, and freely floating devices.
• Scalability to numerous channels necessitates distributed, multi-device systems, moving away from centralized implants.
• Mitigating challenges like tethers, micromotion, and wiring reliability is crucial for these advanced interfaces.

Purpose of the Study:

• To maximize specific absorption rate (SAR)-constrained wireless power transfer efficiency (PTE) for mm-sized receivers in inductive links.
• To investigate chip-scale coil structures for efficient near-field coupling in microsystem integration.
• To develop and validate near-optimal coil geometries for in-CMOS, above-CMOS, and around-CMOS configurations.

Main Methods:

• Developed analytical and simulation models for three chip-scale coil structures: in-CMOS, above-CMOS, and around-CMOS.
• Fabricated prototype coils constrained to a 4x4 mm silicon substrate.
• Validated models through experimental measurements in air and biological tissues, assessing quality factors (Q) and PTE.

Main Results:

• Measured Q factors: 10.5 @450.3 MHz (in-CMOS), 24.61 @85 MHz (above-CMOS), and 26.23 @283 MHz (around-CMOS).
• Demonstrated SAR-constrained maximum PTE in tissue: 1.64% @355.8 MHz (in-CMOS), 2.09% @82.9 MHz (above-CMOS), and 3.05% @318.8 MHz (around-CMOS).
• Quantified tissue loss effects on power transfer efficiency for bio-implant applications.

Conclusions:

• The study presents optimized chip-scale coil designs for efficient wireless power transfer in mm-sized neural implants.
• The developed coil structures and validated models support the advancement of untethered, scalable neural interface systems.
• Results provide critical data for designing future implantable devices with improved power delivery and reduced tissue impact.