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NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Maps.

Alessandro Aimar, Hesham Mostafa, Enrico Calabrese

    IEEE Transactions on Neural Networks and Learning Systems
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    Summary
    This summary is machine-generated.

    NullHop, a novel Convolutional Neural Network (CNN) accelerator, enhances visual processing efficiency by exploiting neuron activation sparsity. This low-power, low-latency design achieves high performance on FPGAs for real-time applications.

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    Area of Science:

    • Computer Engineering
    • Artificial Intelligence
    • Hardware Acceleration

    Background:

    • Convolutional Neural Networks (CNNs) are state-of-the-art for visual processing but are power-intensive.
    • Existing graphical processing units (GPUs) offer limited power efficiency for CNN inference ( < 10 GOp/s/W).
    • Low-power, low-latency solutions are crucial for edge computing and real-time visual tasks.

    Purpose of the Study:

    • To propose NullHop, a flexible and efficient CNN accelerator architecture.
    • To leverage neuron activation sparsity for accelerated computation and reduced memory footprint.
    • To enable high utilization of computing resources for diverse CNN kernel sizes and feature maps.

    Main Methods:

    • Designed a flexible CNN accelerator architecture, NullHop.
    • Implemented NullHop on a Xilinx Zynq Field-Programmable Gate Array (FPGA).
    • Evaluated performance on various CNNs, including VGG16 and VGG19, using postsynthesis simulations.

    Main Results:

    • Achieved over 450 GOp/s for VGG19 at 500 MHz in a 28-nm process.
    • Demonstrated over 368% efficiency by exploiting sparsity.
    • Attained a power efficiency exceeding 3 TOp/s/W within a 6.3 mm² core area.
    • Maintained over 98% utilization of multiply-accumulate units.

    Conclusions:

    • NullHop provides a highly efficient and flexible solution for CNN acceleration.
    • The architecture significantly reduces power consumption and latency for visual processing tasks.
    • Successful FPGA implementation and integration with neuromorphic cameras demonstrate practical usability for real-time interactive systems.