An efficient control flow validation method using redundant computing capacity of dual-processor architecture.

Area of Science:

• Computer Architecture
• Embedded Systems Security
• Hardware Security

Background:

• Microprocessors in safety-critical systems are vulnerable to binary modification and control flow hijacking by attackers.
• Existing run-time validation methods often require significant hardware modifications, posing a design challenge.
• Circuit crosstalk can also lead to erroneous program execution in critical systems.

Purpose of the Study:

• To propose an efficient run-time control flow validation method with minimal hardware modification for safety-critical microprocessors.
• To enhance the security of microprocessors against external attacks and internal circuit crosstalk.
• To validate program execution paths dynamically without substantial performance degradation.

Main Methods:

• Introduced the Dual-Processor Control Flow Validation Method (DCM) leveraging a dual-processor architecture.
• Utilized idle pipeline cycles of a blocked processor for control flow validation by the other processor.
• Incorporated lightweight monitor units, a special dual-processor communication protocol, and a software-based self-validation algorithm.

Main Results:

• The DCM effectively validates control flow at run time by scheduling redundant computing capacity between processors.
• The combined hardware and software approach speeds up validation and protects control flow paths.
• Simulations using GEM5 on ARMv7-A processors show an average performance overhead of less than 22% across SPEC 2006 benchmarks.

Conclusions:

• The proposed DCM offers an efficient and practical solution for run-time control flow validation in safety-critical systems.
• DCM provides robust protection against control flow hijacking with acceptable performance overhead.
• The method demonstrates the feasibility of enhancing microprocessor security through architectural innovations and hybrid validation techniques.