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Related Experiment Video

Updated: Feb 7, 2026

Fabrication and Characterization of Thickness Mode Piezoelectric Devices for Atomization and Acoustofluidics

Fabrication and Characterization of Thickness Mode Piezoelectric Devices for Atomization and Acoustofluidics

Published on: August 5, 2020

CMOS platform for atomic-scale device fabrication.

Tomáš Škereň¹, Nikola Pascher¹, Arnaud Garnier^2,3

¹IBM Research-Zurich, Säumerstrasse 4, 8803 Rüschlikon, Switzerland.

|August 3, 2018

Summary

This summary is machine-generated.

This study introduces a new method for atomic-scale fabrication of dopant devices by integrating scanning tunneling microscopy (STM) with CMOS technology. This approach significantly reduces fabrication complexity and enhances device yield for advanced electronic applications.

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Area of Science:

Materials Science
Nanotechnology
Semiconductor Device Fabrication

Background:

Atomic-scale fabrication methods often require complex processes and ultra-high vacuum, limiting throughput.
Existing techniques struggle with integrating novel fabrication with standard semiconductor manufacturing.

Purpose of the Study:

To develop an integrated fabrication platform for atomic-scale dopant devices.
To overcome limitations of current fabrication methods by combining scanning probe techniques with CMOS compatibility.

Main Methods:

Utilized silicon-on-insulator substrates with a protected Si(001):H surface.
Integrated scanning tunneling microscope (STM) patterning with a CMOS-compatible process flow.
Reduced ultra-high vacuum processing to critical steps.

Main Results:

Demonstrated a streamlined fabrication process for dopant devices.
Successfully reintegrated STM-patterned devices into CMOS workflows.
Achieved full functionality of STM-patterned silicon:phosphorus (Si:P) nanowires via magnetotransport measurements up to room temperature.

Conclusions:

The developed platform overcomes traditional limitations in atomic-scale fabrication.
This integration enables the application of STM-fabricated dopant devices in complex architectures.
The approach shows promise for high-yield, room-temperature operation of nanodevices.