Dynamic switching of a packaged photonic integrated network-on-chip using an FPGA controller

Area of Science:

• Photonics
• Integrated Circuits
• Computer Engineering

Background:

• Photonic integrated networks are crucial for high-speed data communication.
• Dynamic traffic management is essential for efficient network performance.
• Network-on-chip (NoC) architectures offer scalable solutions for interconnecting processing elements.

Purpose of the Study:

• To demonstrate a packaged photonic integrated network-on-chip (NoC).
• To evaluate the performance of the NoC under dynamic packet-switched traffic.
• To investigate the impact of interfering signals on the NoC's power penalty.

Main Methods:

• A packaged photonic integrated NoC based on multi-microrings was designed and fabricated.
• A controller and scheduler were implemented using Field-Programmable Gate Array (FPGA).
• Dynamic packet-switched traffic scenarios with up to three interfering signals at the same wavelength were simulated and tested.

Main Results:

• The dynamic switching of the NoC exhibited a power penalty of approximately 0.5 dB at a Bit Error Rate (BER) of 10^-9.
• The presence of up to three interfering signals induced a power penalty below 1 dB.
• The implemented FPGA controller and scheduler effectively managed dynamic traffic.

Conclusions:

• The demonstrated packaged photonic integrated NoC is suitable for dynamic packet-switched traffic.
• The system shows robust performance with minimal power penalty, even in the presence of wavelength-level interference.
• This technology offers a promising solution for future high-performance computing and data center interconnects.