Weighted p -Bits for FPGA Implementation of Probabilistic Circuits.

Area of Science:

• Computer Science
• Electrical Engineering
• Quantum Computing

Background:

• Probabilistic spin logic is an emerging computing paradigm utilizing probabilistic bits (p-bits).
• These p-bits can be interconnected to form probabilistic circuits (p-circuits) for various computational tasks.
• Existing p-circuits are explored for optimization, inference, and implementing Boolean functions in reverse (invertible mode).

Purpose of the Study:

• To present a scalable Field-Programmable Gate Array (FPGA) implementation of invertible p-circuits.
• To introduce a novel 'weighted' p-bit incorporating stochastic units and localized memory.
• To demonstrate the application of these weighted p-circuits to problems beyond standard invertible Boolean logic.

Main Methods:

• Development of a scalable FPGA architecture for probabilistic spin logic circuits.
• Implementation of a weighted probabilistic bit (p-bit) combining stochasticity and memory.
• Design of a generalized tile of weighted p-bits for flexible problem mapping.

Main Results:

• Successful hardware implementation of invertible p-circuits on an FPGA.
• Demonstration of weighted p-bits capable of solving problems via reverse Boolean logic.
• Application of the generalized tile to solve an instance of the NP-complete subset sum problem.

Conclusions:

• The proposed FPGA implementation offers a scalable approach to probabilistic spin logic.
• Weighted p-bits provide a versatile hardware primitive for complex computational problems.
• Invertible p-circuits show promise for efficiently tackling optimization and NP-complete problems.