The Balancing Act in Ferroelectric Transistors: How Hard Can It Be?

Area of Science:

• Materials Science
• Electrical Engineering
• Solid State Physics

Background:

• Dimensional scaling limitations in CMOS technology necessitate alternative device architectures.
• Ferroelectric materials offer a promising route for enhanced gate control via positive feedback mechanisms.

Purpose of the Study:

• To elaborate on two ferroelectric-based device architectures: negative-capacitance field-effect transistor (NC-FET) and piezoelectric field-effect transistor (π-FET).
• To compare the operational principles and performance of NC-FET and π-FET based on existing literature.

Main Methods:

• Review and comparison of operational principles for NC-FET and π-FET.
• Analysis of material property requirements for optimal performance in each device type.
• Literature-based performance evaluation regarding subthreshold swing, on-current, and speed.

Main Results:

• NC-FETs demonstrate superior subthreshold swing and on-current compared to π-FETs.
• Optimal NC-FET performance requires "hard" ferroelectric materials with specific remnant polarization (e.g., Hafnium-Zirconate).
• π-FETs require ferroelectric materials with a high piezoelectric coefficient and large polarization-field loop (e.g., lead-zirconate-titanate), offering higher speed potential.

Conclusions:

• NC-FETs face speed limitations due to large polarization changes, while π-FETs are faster but may not match NC-FETs in other metrics.
• A hybrid approach combining NC-FET and π-FET architectures on a single chip, utilizing ferroelectric materials with high piezocoefficient, is proposed for future low-power CMOS applications.