Calibration method of overlay measurement error caused by asymmetric mark

Area of Science:

• Semiconductor Manufacturing
• Metrology
• Lithography

Background:

• Scaling semiconductor process nodes to sub-10-nm demands increasingly stringent overlay accuracy for on-product performance monitoring.
• Asymmetric overlay marks generated during lithography introduce measurement errors that vary even within the same process or lot.
• Current wafer alignment data correction methods leave residual errors due to differing mark structures and process sensitivities.

Purpose of the Study:

• To propose and validate a novel method for calibrating overlay measurement errors stemming from asymmetric marks.
• To enhance the precision of overlay measurements in advanced semiconductor fabrication.
• To investigate the impact of mark asymmetry on overlay measurement inaccuracies.

Main Methods:

• Developing a new calibration technique based on the correlation between overlay mark and single-layer mark measurement data.
• Utilizing simulations with various asymmetric mark types to verify the proposed method's efficacy.
• Comparing the new method against existing techniques that rely on wafer alignment data.

Main Results:

• The proposed method effectively calibrates overlay measurement errors caused by asymmetric marks.
• Simulations demonstrated the validity of the approach across different asymmetric mark designs.
• The technique shows significant potential for improving overall overlay measurement accuracy.

Conclusions:

• The developed method offers a viable solution for correcting overlay measurement errors linked to asymmetric lithography marks.
• Accurate overlay measurement is critical for maintaining on-product performance in advanced semiconductor manufacturing.
• Understanding and mitigating errors from mark asymmetry is essential for process control and yield improvement.