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Related Experiment Video

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Nano-Programmable Logics Based on Double-Layer Anti-Facing Memristors.

Jaeheum Lee1, Jason K Eshraghian2, Minyoung Jeong1

  • 1Department of EE, Chungbuk National University, 1 Chungdae-ro Seowon-gu, Cheongju, 28644, S. Korea.

Journal of Nanoscience and Nanotechnology
|November 25, 2018
PubMed
Summary
This summary is machine-generated.

We introduce a novel nano-programmable logic array (PLA) using anti-facing memristors. This design enhances system-on-chip (SoC) performance by reducing propagation delay by 70%.

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Area of Science:

  • Nanoscience and Nanotechnology
  • Electrical Engineering and Computer Science
  • Materials Science

Background:

  • Memristors, theorized by Chua in 1971, are two-terminal devices whose resistance depends on charge flow history.
  • High-density crossbar arrays of nanoscale memristors are emerging architectures for system-on-chip (SoC) implementation, offering simplified structures and improved performance.
  • Memristors' nanoscale switching capability, altering resistance between high and low states, makes them suitable for advanced logic devices.

Purpose of the Study:

  • To propose a new nano-programmable logic array (PLA) device utilizing an anti-facing double-layer memristor array.
  • To integrate AND and OR planes onto a single layer within a vertically stacked crossbar architecture.
  • To leverage the anti-facing memristor configuration for simplified pull-up and pull-down register determination.

Main Methods:

  • Designed a novel PLA architecture comprising vertically stacked, anti-facing memristor crossbar layers.
  • Merged the AND and OR planes onto the same layer, forming a 5-layer structure: bottom metal, memristive, intermediate metal, anti-facing memristive, and top metal layers.
  • Utilized the intermediate metal layer as the output of the AND plane and the input for the OR plane, enabling shared input/output nodes.

Main Results:

  • The proposed architecture significantly reduces the propagation delay of the AND plane by 70% through shared OR plane input wires.
  • The anti-facing memristor configuration simplifies the determination of appropriate values for pull-up and pull-down registers.
  • Achieved a compact and efficient logic device suitable for advanced SoC applications.

Conclusions:

  • The novel anti-facing double-layer memristor array offers a promising architecture for next-generation nano-programmable logic arrays.
  • This design enhances SoC performance by minimizing signal propagation delays and simplifying device configuration.
  • The integrated AND-OR plane structure represents a significant advancement in memristor-based logic device development.