Run-time reconfigurable adaptive LDPC coding for optical channels.

Area of Science:

• Coding Theory
• Digital Communications
• Optical Communications

Background:

• Low-Density Parity-Check (LDPC) codes are crucial for error correction in modern communication systems.
• Maximizing code girth is essential for LDPC code performance, especially in challenging channels.
• Existing hardware implementations often lack flexibility and efficiency for diverse applications.

Purpose of the Study:

• To propose a novel class of large-girth Quasi-Cyclic LDPC (QC-LDPC) codes.
• To design a unified, reconfigurable Field-Programmable Gate Array (FPGA) architecture for these codes.
• To evaluate the performance of the proposed codes and architecture in Additive White Gaussian Noise (AWGN) and Free-Space Optical (FSO) channels.

Main Methods:

• Design of large-girth QC-LDPC codes with code rates from 0.5 to 0.8.
• Development of a unified, run-time reconfigurable FPGA-based architecture for LDPC encoding and decoding.
• Implementation of code shortening to bridge rate gaps.
• FPGA emulation for performance evaluation in AWGN channels.
• Testing in a spatial light modulator (SLM)-based FSO channel emulator.

Main Results:

• Demonstrated signal-to-noise ratio (SNR) limits of -1 dB to 2.2 dB at a Bit Error Rate (BER) of 10^-12 in AWGN channels.
• Achieved post-Forward Error Correction (FEC) BER below 10^-8 in medium atmospheric turbulence for FSO applications, without interleaving or adaptive optics.
• The unified architecture supports a wide range of code rates (0.5-0.8).

Conclusions:

• The proposed large-girth QC-LDPC codes and unified FPGA architecture offer efficient and flexible error correction.
• The design is well-suited for both fiber optics and Free-Space Optical (FSO) communication systems.
• The architecture demonstrates robust performance, even in challenging FSO channel conditions like atmospheric turbulence.