Efficient Synapse Memory Structure for Reconfigurable Digital Neuromorphic Hardware.

Area of Science:

• Computer Science
• Neuroscience
• Electrical Engineering

Background:

• Spiking Neural Networks (SNNs) offer efficient information processing using binary spikes and temporal dynamics.
• Conventional Von Neumann architectures face limitations when running SNNs, driving interest in dedicated hardware accelerators with on-chip memory.

Purpose of the Study:

• To propose an efficient synapse memory structure for SNN hardware accelerators.
• To reduce hardware resource usage while maintaining SNN performance and network size.

Main Methods:

• Implemented synapse memory reduction using presynaptic weight scaling.
• Utilized axonal/neuronal offsets for multi-layer implementation on a single memory array.
• Introduced a transposable memory addressing scheme for accelerated Spike-Timing-Dependent Plasticity (STDP) learning.

Main Results:

• Developed an SNN ASIC chip using a 65 nm CMOS process based on the proposed scheme.
• Achieved up to 200X speedup compared to CPU execution.
• Demonstrated energy efficiency of 15.2 pJ/SOP with 53 mW power consumption at 100 MHz.

Conclusions:

• The proposed efficient synapse memory structure significantly enhances SNN hardware accelerator performance and energy efficiency.
• The design effectively reduces hardware resource requirements, making SNNs more viable for practical implementation.
• The developed ASIC chip validates the proposed scheme's effectiveness for high-speed, low-power SNN computation.