Low Cost Interconnected Architecture for the Hardware Spiking Neural Networks

Area of Science:

• Computer Engineering
• Artificial Intelligence
• Neuroscience

Background:

• Hardware implementation of Spiking Neural Networks (SNNs) requires efficient methods for managing neuron interconnections.
• Existing architectures often face challenges with high hardware overhead and routing performance, limiting scalability.

Purpose of the Study:

• To propose a novel low cost interconnected architecture (LCIA) for efficient neuron interconnections in hardware SNNs.
• To achieve efficient routing performance with minimal hardware overhead, enabling scalable SNN hardware.

Main Methods:

• The proposed LCIA utilizes an all-to-all connection strategy for multi-layer SNNs.
• A Networks-on-Chip (NoC) router is employed as the core component, featuring an effective scheduler for irregular spike traffic.
• The router is designed for rapid request identification, prompt arbitration, and equitable service for diverse network traffic.

Main Results:

• The LCIA effectively manages intercommunication in multi-layer neural networks.
• The architecture demonstrates low hardware overhead, contributing to the scalability of hardware SNNs.
• The proposed router achieves efficient traffic handling despite irregular spike patterns.

Conclusions:

• The LCIA presents a cost-effective and efficient solution for hardware SNN interconnections.
• The proposed NoC-based approach enhances the scalability of SNN hardware implementations.
• This architecture addresses key challenges in routing performance and hardware overhead for SNNs.