Improving ESD Protection Robustness Using SiGe Source/Drain Regions in Tunnel FET

Area of Science:

• Semiconductor Device Physics
• Materials Science
• Electrical Engineering

Background:

• Tunnel field-effect transistors (TFETs) are emerging as promising candidates for electrostatic discharge (ESD) protection in advanced integrated circuits.
• Silicon-germanium (SiGe) material engineering has shown potential for enhancing TFET performance.

Purpose of the Study:

• To propose and evaluate a novel TFET incorporating SiGe source/drain (S/D) regions for improved ESD protection.
• To investigate the impact of SiGe S/D integration on the ESD characteristics of TFETs.

Main Methods:

• Technology Computer-Aided Design (TCAD) simulations were employed to model and analyze the proposed SiGe S/D TFET.
• Transmission Line Pulsing (TLP) stressing conditions were used to assess the ESD robustness of the device.

Main Results:

• The proposed SiGe S/D TFET exhibited a 35% reduction in triggering voltage compared to conventional Si S/D TFETs.
• A 17% increase in failure current was observed for the SiGe S/D TFET under TLP stress.
• Physical insights into the ESD enhancement mechanisms provided by SiGe S/D regions were discussed.

Conclusions:

• The integration of SiGe S/D regions significantly enhances the ESD protection capabilities of TFETs.
• The SiGe S/D TFET presents a viable solution for robust ESD protection in next-generation semiconductor technologies.