Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture

Area of Science:

• Semiconductor device physics
• Materials science

Background:

• Tunnel field-effect transistors (TFETs) are limited by low on-state current, hindering practical applications.
• Optimizing TFET performance is crucial for next-generation electronics.

Purpose of the Study:

• To enhance TFET performance by combining energy-band engineering of InAs/Si heterojunction with a source-pocket concept.
• To develop an analytical model for predicting TFET performance.

Main Methods:

• Fabrication and characterization of a novel TFET structure integrating InAs/Si heterojunction and source-pocket design.
• Development of an analytical potential model to calculate tunneling current.
• Comparison of model predictions with numerical simulations.

Main Results:

• The proposed TFET design demonstrates significantly improved tunnel on-state current and subthreshold swing.
• The developed analytical model shows good agreement with numerical simulations, validating its accuracy.
• The model enables faster simulations for TFET-based circuit investigations.

Conclusions:

• The integrated InAs/Si heterojunction and source-pocket design effectively boosts TFET performance.
• The validated analytical model offers an efficient tool for further TFET research and circuit design.
• This work paves the way for more practical and high-performance TFET applications.