In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs

Area of Science:

• Computer Engineering
• Memory Systems
• Semiconductor Devices

Background:

• 3D-stacked dynamic random access memory (DRAM) offers high capacity and bandwidth but faces latency issues, known as the memory wall.
• Existing latency hiding schemes are insufficient for high-performance, high-capacity 3D-stacked DRAM systems.
• In-DRAM cache architectures are proposed for cost-effective implementation in 3D-stacked DRAM, but management methods are underdeveloped.

Purpose of the Study:

• To develop novel management algorithms for in-DRAM caches in 3D-stacked DRAM.
• To address the critical need for reduced latency and power consumption in advanced memory devices.
• To enhance the performance of high-capacity memory systems by optimizing cache management.

Main Methods:

• Proposed two new management algorithms specifically designed for in-DRAM caches.
• Utilized computing system simulations to evaluate the proposed algorithms.
• Focused on improving latency and power efficiency in 3D-stacked DRAM.

Main Results:

• Demonstrated significant improvements in the energy delay product (EDP) of 3D-stacked DRAM devices.
• Achieved up to a 67% improvement in EDP through the new management algorithms.
• Validated the effectiveness of the proposed algorithms in reducing latency and power.

Conclusions:

• The developed in-DRAM cache management algorithms effectively reduce latency and power consumption in 3D-stacked DRAM.
• These algorithms offer a practical solution to the memory wall problem in high-capacity memory systems.
• The proposed methods provide a pathway to more energy-efficient and lower-latency memory technologies.