FPGA-Based Hybrid-Type Implementation of Quantized Neural Networks for Remote Sensing Applications

Area of Science:

• Computer Vision
• Hardware Acceleration
• Remote Sensing

Background:

• Convolutional Neural Networks (CNNs) show great promise in remote sensing but face hardware deployment challenges.
• Floating-point operations in CNNs are resource-intensive, limiting their use in power-constrained hardware like FPGAs and ASICs.
• Real-time processing of remote sensing data demands efficient hardware implementations.

Purpose of the Study:

• To optimize CNN hardware design for remote sensing applications using low bit-width integer quantization.
• To reduce the resource and power consumption of CNNs for deployment on FPGAs and ASICs.
• To maintain high accuracy in quantized CNN models for remote sensing image classification.

Main Methods:

• A symmetric quantization scheme-based hybrid-type inference method was developed to replace floating-point precision with low bit-width integers.
• A training approach was introduced to mitigate accuracy degradation in the quantized CNN.
• A low bit-width processing engine (PE) and a fused-layer PE were designed for FPGA implementation, supporting Batch-Normalization and LeakyRelu.

Main Results:

• The 8-bit quantized CNN model achieved accuracy comparable to floating-point models on the MSTAR dataset, with only a ~1% drop.
• FPGA testing confirmed accuracy consistent with GPU results.
• Significant reductions in FPGA resource utilization were observed: 46.21% for LUTs, 43.84% for FFs, 45% for DSPs, and 51% for BRAMs compared to floating-point implementations.

Conclusions:

• Quantization to low bit-width integers is an effective strategy for deploying CNNs in resource-constrained hardware for remote sensing.
• The proposed quantization method and hardware designs enable efficient, real-time remote sensing image classification on FPGAs.
• This approach significantly reduces hardware resource consumption without compromising classification accuracy.