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GeCo: Classification Restricted Boltzmann Machine Hardware for On-Chip Semisupervised Learning and Bayesian

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    This study introduces a hardware accelerator for classification restricted Boltzmann machines (ClassRBM) that enhances semisupervised learning and Bayesian inference. The novel asymmetric contrastive divergence (ACD) algorithm significantly improves ClassRBM accuracy and speed for real-time data processing.

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    Area of Science:

    • Artificial Intelligence
    • Machine Learning
    • Hardware Acceleration

    Background:

    • Probabilistic Bayesian inference and semisupervised learning are increasingly vital for real-time data analysis.
    • Classification Restricted Boltzmann Machines (ClassRBM) offer hardware implementation advantages over backpropagation networks but suffer from lower accuracy.
    • Existing training algorithms like contrastive divergence (CD) show suboptimal performance with advanced ClassRBM architectures.

    Purpose of the Study:

    • To develop a hardware accelerator for ClassRBM with integrated semisupervised learning and Bayesian inference capabilities.
    • To enhance the accuracy of ClassRBM, particularly in semisupervised learning scenarios.
    • To introduce a novel training algorithm that overcomes the limitations of conventional methods for ClassRBM.

    Main Methods:

    • Implementation of a ClassRBM-based hardware accelerator featuring on-chip semisupervised learning and Bayesian inference.
    • Proposal of a multi-neuron-per-class (multi-NPC) voting scheme to boost ClassRBM accuracy.
    • Development and application of an asymmetric contrastive divergence (ACD) training algorithm as an alternative to the standard CD algorithm.

    Main Results:

    • The proposed ACD algorithm demonstrated a 5.82% higher inference accuracy in supervised learning and a 12.78% higher accuracy in 1% labeled semisupervised learning compared to the conventional CD algorithm.
    • Experimental validation on a Modified National Institute of Standards and Technology dataset using a field-programmable gate array (FPGA) confirmed the accuracy improvements.
    • The GeCo ver.2 hardware accelerator achieved a 349.04x speedup over C simulation on a CPU.

    Conclusions:

    • The novel ACD training algorithm effectively enhances the accuracy of multi-NPC ClassRBM, especially in semisupervised learning contexts.
    • The ClassRBM hardware accelerator provides a significant speed advantage for real-time Bayesian inference and semisupervised learning tasks.
    • This work presents a promising approach for efficient and accurate on-chip machine learning inference.