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Enhancing Sensor Network Security with Improved Internal Hardware Design.

Weizheng Wang1,2, Zhuo Deng3, Jin Wang4,5,6

  • 1School of Computer & Communication Engineering, Changsha University of Science & Technology, Changsha 410114, China. peakexpe@csust.edu.cn.

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Summary
This summary is machine-generated.

This study introduces a secure scan test architecture for Internet-of-Things (IoT) cryptographic chips. The design prevents sensitive key information leakage during testing, enhancing overall chip security.

Keywords:
Internet-of-Thingscryptographic chipsinformation securitysensor networkssensors

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Area of Science:

  • Computer Engineering
  • Cybersecurity
  • Embedded Systems

Background:

  • Internet-of-Things (IoT) devices increasingly rely on sensors, necessitating robust security for their cryptographic chips.
  • Scan design, a Design-for-Testability (DFT) technique, improves chip testability but can introduce security vulnerabilities by enabling sensitive data leakage.
  • Noninvasive attacks targeting scan chains pose a significant threat to the confidentiality of cryptographic keys in hardware implementations.

Purpose of the Study:

  • To propose a novel secure scan test architecture for cryptographic chips used in IoT sensor networks.
  • To mitigate security risks associated with scan design, specifically noninvasive attacks that exploit scan chains.
  • To ensure the integrity and confidentiality of cryptographic keys during chip testing and operation.

Main Methods:

  • Implemented a scan chain reset mechanism by integrating a mode-switching detection signal with the scan cell reset input.
  • Enforced restrictions on loading secret keys into scan chains during test mode to prevent test-mode-only scan attacks.
  • Disabled shift operations in functional mode to counter scan attacks that occur during normal operation.

Main Results:

  • The proposed architecture effectively deters mode-switching based noninvasive attacks by erasing scan chain contents upon mode transition.
  • Loading secret keys into scan chains during test mode is successfully prohibited, thwarting test-mode-only scan attacks.
  • Scan attacks during functional mode are prevented by disabling shift operations, ensuring continuous security.

Conclusions:

  • The developed secure scan test architecture significantly enhances the security of cryptographic chips for IoT sensor networks against scan-based attacks.
  • The proposed design achieves robust security with a minimal area overhead, making it practical for resource-constrained embedded systems.
  • This approach provides a viable solution for securing hardware cryptographic implementations against emerging noninvasive threats.