A 6.6 ps RMS resolution time-to-digital converter using interleaved sampling method in a 28 nm FPGA.

Area of Science:

• Digital electronics
• Integrated circuit design

Background:

• Time-to-digital converters (TDCs) are crucial for precise timing measurements in various applications.
• Existing TDC designs face limitations in achieving high precision due to cell delay constraints.

Purpose of the Study:

• To propose and evaluate a novel interleaved sampling method for TDC implementation in field-programmable gate arrays (FPGAs).
• To enhance TDC precision beyond the inherent cell delay limits.

Main Methods:

• Implementation of an adaptive logic module structure within a 28 nm FPGA.
• Development and application of an interleaved sampling technique with bin realignment.
• Sampling tap status twice per physical channel to improve precision.

Main Results:

• Successful implementation of two TDC channels on a 28 nm Cyclone-V FPGA.
• Achieved a post-calibration timing resolution of 6.6 ps root mean square (RMS).
• Demonstrated a resolution of 5.8 ps per least significant bit (LSB).

Conclusions:

• The proposed interleaved sampling method effectively enhances TDC precision.
• The technique enables TDCs to achieve timing resolutions superior to cell delay limitations.
• FPGA-based TDCs can achieve sub-picosecond timing resolution with this method.