Fan-Out Wafer and Panel Level Packaging as Packaging Platform for Heterogeneous Integration

Area of Science:

• Microelectronics
• Advanced Packaging Technologies
• Energy Harvesting Systems

Background:

• Fan-out wafer level packaging (FOWLP) and panel level packaging (PLP) are emerging trends in microelectronics manufacturing.
• These technologies support heterogeneous integration, including multiple die, passive components, and package-on-package (PoP) approaches.
• Current manufacturing scales up to 300/330 mm wafers, with larger formats like PLP being explored for increased productivity and reduced costs.

Purpose of the Study:

• To develop an application-specific integrated circuit (ASIC) package using FOWLP and PLP approaches.
• To integrate surface mount device (SMD) capacitors within the package.
• To demonstrate the feasibility of scaling these packaging technologies for miniaturized energy harvester systems.

Main Methods:

• The study utilized both FOWLP and PLP approaches for ASIC package development with integrated SMD capacitors.
• Process development and proof of concept were initially performed on a 200 mm wafer.
• The technology was subsequently scaled to a 457 × 305 mm panel size using identical materials and processes.

Main Results:

• Successful proof of concept for FOWLP and PLP packaging of an ASIC with integrated capacitors.
• Demonstrated scalability of the packaging process from wafer to panel level.
• Validated the low-cost, large-area manufacturing potential of the developed approach.

Conclusions:

• FOWLP and PLP are suitable for packaging highly miniaturized energy harvester systems, including piezo-based harvesters, power management units, and supercapacitors.
• The developed packaging process is scalable and cost-effective for large-area manufacturing.
• These advanced packaging technologies offer significant opportunities for miniaturization and heterogeneous integration in microelectronics.