Tight Evaluation of Real-Time Task Schedulability for Processor's DVS and Nonvolatile Memory Allocation

Area of Science:

• Computer Science
• Electrical Engineering
• Embedded Systems

Background:

• Real-time systems require efficient power management to extend battery life and reduce operational costs.
• Hybrid memory architectures (DRAM and NVRAM) offer potential for power savings but introduce complexity in task scheduling and memory management.
• Existing power-saving techniques often overlook the interplay between processor states and memory access patterns.

Purpose of the Study:

• To develop an integrated power-saving approach for real-time systems.
• To optimize task placement in hybrid memory (DRAM and NVRAM) alongside processor voltage scaling.
• To minimize power consumption without violating real-time task deadlines.

Main Methods:

• Developed a combined task model integrating processor voltage scaling and memory placement (DRAM/NVRAM).
• Incorporated worst-case execution time (WCET) analysis considering processor-memory overlap delays.
• Implemented selective power-saving strategies for both processor and memory components.

Main Results:

• Achieved significant power consumption reduction in real-time systems, ranging from 18% to 88%.
• Demonstrated the effectiveness of the integrated approach in balancing power efficiency and deadline adherence.
• Validated the model's accuracy in evaluating WCET with processor-memory interaction.

Conclusions:

• The proposed approach offers a robust solution for power management in real-time systems utilizing hybrid memory.
• Integrating task memory placement with voltage scaling provides substantial energy savings.
• Accurate WCET evaluation, including processor-memory delays, is crucial for effective power optimization.