Fine-Grained Power Gating Using an MRAM-CMOS Non-Volatile Flip-Flop

Area of Science:

• Integrated Circuits
• Semiconductor Devices
• Non-Volatile Memory

Background:

• Conventional flip-flops require constant power, leading to data loss during power-down events.
• Non-volatile flip-flops (NVFFs) aim to retain data without power, but often suffer from significant area and energy overheads.
• Existing NVFF designs struggle to balance performance, area efficiency, and energy consumption.

Purpose of the Study:

• To propose an area-efficient non-volatile flip-flop (NVFF) with minimized overhead.
• To introduce optimization strategies for enhancing the NVFF's practical application.
• To evaluate the performance of the proposed NVFF in a 10 nm technology node.

Main Methods:

• Integration of two minimum-sized Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and two magnetic tunnel junction (MTJ) devices with a conventional D flip-flop.
• Implementation of area overhead minimization by reusing parts of the D flip-flop and energy overhead reduction via a current-reuse technique.
• Development of two optimization strategies: module-based placement during design and dynamic write pulse modulation at runtime.

Main Results:

• The proposed NVFF achieves a 6.9% area overhead compared to conventional flip-flops.
• Demonstrated a 4.1x reduction in area and a 1.5x reduction in energy compared to prior state-of-the-art NVFFs.
• Module-based placement improved area and energy by 2-18x, while pulse modulation offered further energy savings.

Conclusions:

• The proposed NVFF design offers a significant improvement in area and energy efficiency for non-volatile memory applications.
• The presented optimization strategies effectively minimize overheads, making NVFFs more practical for implementation.
• This work provides a promising solution for low-power integrated circuits requiring data retention during power interruptions.