All-Inkjet-Printed Vertical Heterostructure for Wafer-Scale Electronics.

Area of Science:

• Materials Science
• Electronics Engineering
• Nanotechnology

Background:

• Inkjet printing offers a scalable and cost-effective method for fabricating electronic devices.
• Vertical Schottky barrier transistors are crucial for low-power electronics due to their efficient current modulation.
• Developing large-area, high-performance printed electronics remains a significant challenge.

Purpose of the Study:

• To fabricate all-inkjet-printed vertical Schottky barrier (SB) transistors and logic gates on a large-area substrate.
• To investigate the performance and stability of these printed devices.
• To demonstrate the feasibility of using these transistors for low-power integrated circuits.

Main Methods:

• Fabrication of vertical SB transistors using inkjet-printed indium-gallium-zinc-oxide (IGZO) semiconductor, reduced graphene oxide (rGO) source electrode, indium-tin-oxide (ITO) drain electrode, and ion-gel dielectric.
• Utilized a coplanar gate geometry for the ion-gel dielectric.
• Characterized device performance including current density, on-off ratio, and stability under operational and environmental stress.

Main Results:

• Achieved high current density (2.0 A·cm⁻²) and on-off current ratio (10⁶) in vertical SB transistors.
• Demonstrated effective modulation of Schottky barrier height (~0.5 eV) with low gate voltage (<2 V) due to high ion-gel dielectric capacitance.
• Successfully fabricated all-inkjet-printed logic gates (NOT, NAND, NOR) with excellent operational and environmental stability.

Conclusions:

• All-inkjet printing enables the large-area fabrication of high-performance vertical SB transistors and logic circuits.
• The developed devices exhibit promising characteristics for low-power electronic applications.
• The simple device architecture and printing process facilitate the integration of complex logic functions on a single substrate.