Van der Waals negative capacitance transistors.

Area of Science:

• Materials Science
• Semiconductor Physics
• Nanotechnology

Background:

• The Boltzmann distribution limits energy efficiency in conventional MOSFETs.
• Negative capacitance FETs (NC-FETs) offer a path to overcome the thermionic limit for ultra-low-power electronics.

Purpose of the Study:

• To demonstrate steep-slope NC-FETs utilizing 2D MoS2 and CuInP2S6 (CIPS) van der Waals heterostructures.
• To evaluate the performance of these vdW NC-FETs for low-power and flexible electronic applications.

Main Methods:

• Fabrication of van der Waals heterostructures using MoS2 and CIPS.
• Characterization of electrical properties, including subthreshold swing (SS) and hysteresis.
• Measurement of voltage gain in NC-FET logic inverters.
• Testing of flexible NC-FETs under bending conditions.

Main Results:

• Achieved average SS below the Boltzmann limit (<60 mV/decade) over seven decades of drain current, with a minimum SS of 28 mV/decade.
• Demonstrated negligible hysteresis for CIPS thickness < 20 nm.
• Measured a voltage gain of 24 for a vdW NC-FET logic inverter.
• Showcased flexible vdW NC-FETs with SS < 60 mV/decade under bending radii down to 3.8 mm.

Conclusions:

• The developed vdW NC-FETs effectively overcome the Boltzmann limit, paving the way for ultra-low-power electronics.
• The demonstrated performance and flexibility highlight the potential of MoS2/CIPS vdW heterostructures for next-generation electronic devices.