Fine-time measurement circuit based on 180° phase-shifted clock sampling in time-to-digital converters

Dead time is an important parameter in time-to-digital converters, which is the significant time measure circuit. To reduce the dead time, this note proposes a new fine-time measurement circuit. In this configuration, two clocks having a phase difference of 180° are used to sample the signals passing through the delay chain, and their average is taken as the final measurement result. The experimental results demonstrate that the dead time of the proposed circuit is observed to be 1.25 ns at 800 MHz clock and the circuit logic resource consumption of the proposed circuit is reduced by approximately 25% compared to other methods.