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A Real-world What-Where-When Memory Test
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A novel application of breadth first algorithm for achieving collision free memory mapping.

Saeed Ur Rehman1, Saeed Ehsan Awan1, Fazel Rehman Mumtaz2

  • 1Department of Electrical and Computer Engineering, COMSATS University Islamabad, Attock, Pakistan.

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|August 16, 2019
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Summary
This summary is machine-generated.

This study addresses memory access conflicts in Turbo decoders for high-speed communication devices. A breadth-first technique optimizes decoder architecture by resolving collisions during parallel processing.

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Area of Science:

  • Electrical Engineering
  • Computer Science
  • Telecommunications

Background:

  • Modern communication devices rely on error correction codes like Turbo and Low-Density Parity-Check (LDPC) codes.
  • High data rates in these devices necessitate parallel processing for Turbo and LDPC decoders.
  • Parallel architectures introduce memory conflict issues, hindering optimal performance.

Purpose of the Study:

  • To resolve memory access conflicts in Turbo decoder architectures.
  • To propose an optimized architecture for efficient parallel processing.
  • To enhance the performance of error correction in communication systems.

Main Methods:

  • Application of a breadth-first search technique.
  • Utilizing transportation modeling for problem analysis.
  • Developing an optimized architecture to mitigate memory collisions.

Main Results:

  • Successfully identified and addressed the memory collision issue in Turbo decoders.
  • Demonstrated an optimized architecture for simultaneous memory bank access.
  • Improved efficiency in parallel decoding processes.

Conclusions:

  • The breadth-first technique effectively solves memory conflicts in Turbo decoders.
  • Optimized architectures are crucial for high-performance communication systems.
  • This approach enhances the reliability and speed of error correction in smart devices.