A low-cost concurrent TSV test architecture with lossless test output compression scheme.

Area of Science:

• Electrical Engineering
• Materials Science
• Computer Engineering

Background:

• Traditional integrated circuit (IC) design faces challenges migrating to three-dimensional integrated circuits (3D-ICs).
• Through-silicon-vias (TSVs) in 3D-ICs are susceptible to latent defects like resistive opens and bridges due to thermal stress.
• These defects degrade electrical performance by increasing resistance-capacitance (RC) delay, necessitating improved reliability and yield solutions.

Purpose of the Study:

• To propose a new TSV test architecture for 3D-ICs.
• To reduce test time, hardware overhead, and peak current consumption in TSV testing.
• To enhance the reliability and yield of 3D-ICs by addressing latent defects.

Main Methods:

• Developed a novel TSV test architecture for 3D-ICs.
• Implemented a single test-clock-period approach to combine test results and defect type classification.
• Introduced block-based concurrent testing to optimize test time by dividing the die into concurrent blocks.

Main Results:

• The proposed architecture successfully transfers combined test output (test result and defect type) in a single test-clock-period.
• Achieved substantial reductions in test time and hardware overhead.
• Maintained reasonable peak power consumption suitable for mass production without compromising test quality.

Conclusions:

• The novel TSV test architecture significantly improves the efficiency and cost-effectiveness of 3D-IC testing.
• This approach offers a viable solution for enhancing the reliability and yield of 3D-ICs in mass production.
• The method effectively addresses the challenges posed by latent defects in TSVs.