A Hardware Implementation of SNN-Based Spatio-Temporal Memory Model.

Area of Science:

• Neuroscience
• Computer Engineering
• Artificial Intelligence

Background:

• Human brain memory simulation using hardware is a long-standing challenge.
• Understanding brain memory organization is crucial for developing advanced AI.
• Existing memory models offer insights but require hardware-specific adaptations.

Purpose of the Study:

• To emulate and analyze associative and episodic memory using a spatio-temporal memory (STM) model.
• To adapt the STM model for practical hardware implementation.
• To fine-tune the network parameters of the implemented STM model on FPGA.

Main Methods:

• Adoption of the spatio-temporal memory (STM) model as a reference architecture.
• Hardware network architecture design based on the STM model.
• Implementation of the memory model on Field-Programmable Gate Arrays (FPGA).
• Experimental fine-tuning of network parameters on the deployed FPGA system.

Main Results:

• Successful hardware emulation of associative and episodic memory functions.
• Demonstration of a functional STM network implemented on FPGA.
• Identification of key parameters for optimizing the hardware memory network performance.

Conclusions:

• The spatio-temporal memory (STM) model can be effectively implemented on FPGA for brain-inspired computing.
• Hardware emulation provides a viable approach for studying complex memory functions.
• Further optimization of FPGA-based memory networks is possible through parameter tuning.