Interfacial Silicide Formation and Stress Evolution during Sputter Deposition of Ultrathin Pd Layers on a-Si

Synchrotron experiments combining real-time stress, X-ray diffraction, and X-ray reflectivity measurements, complemented by in situ electron diffraction and photon electron spectroscopy measurements, revealed a detailed picture of the interfacial silicide formation during deposition of ultrathin Pd layers on amorphous silicon. Initially, an amorphous Pd₂Si interlayer is formed. At a critical thickness of 2.3 nm, this layer crystallizes and the resulting volume reduction leads to a tensile stress buildup. The [111] textured Pd₂Si layer continues to grow up to a thickness of ≈3.7 nm and is subsequently covered by a Pd layer with [111] texture. The tensile stress relaxes already during Pd₂Si growth. A comparison between the texture formation on SiO and a-Si shows that the silicide layer serves as a template for the Pd layer, resulting in a surprisingly narrow texture of only 3° after 800 s Pd deposition. The texture formation of Pd and Pd₂Si can be explained by the low lattice mismatch between Pd(111) and Pd₂Si(111). The combined experimental results indicate a similar interface formation mechanism for Pd on a-Si and c-Si, whereas the resulting silicide texture depends on the Si surface. A new strain relaxation mechanism via grain boundary diffusion is proposed, taking into account the influence of the thickness-dependent crystallization on the material transport through the silicide layer. In combination with the small lattice mismatch, the grain boundary diffusion facilitates the growth of Pd clusters, explaining thus the well-defined thickness of the interfacial silicide layer, which limits the miniaturization of self-organized silicide layers for microelectronic devices.