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Dipole coupled magnetic quantum-dot cellular automata-based efficient approximate nanomagnetic subtractor and adder
Santhosh Sivasubramani1, Venkat Mattela1, Chandrajit Pal1
1Advanced Embedded Systems and IC Design Laboratory, Department of Electrical Engineering, Indian Institute of Technology (IIT), Hyderabad 502285, India.
Nanotechnology
|September 25, 2019
Summary
This study introduces a novel approximate nanomagnetic (APN) design for adders and subtractors using magnetic quantum-dot cellular automata. The new architecture significantly reduces nanomagnets and clock cycles for efficient computing.
Area of Science:
- Nanotechnology
- Computer Architecture
- Quantum Computing
Background:
- Magnetic quantum-dot cellular automata (MQCA) offer a promising platform for low-power computing.
- Existing MQCA designs for arithmetic circuits can be complex and resource-intensive.
Purpose of the Study:
- To propose a novel dipole-coupled magnetic quantum-dot cellular automata-based approximate nanomagnetic (APN) architectural design for subtractor and adder circuits.
- To introduce a runtime reconfigurable APN architecture using a minimal number of nanomagnets.
- To enhance add/sub operations through shape anisotropy and a fixed input majority gate.
Main Methods:
- Design and simulation of APN architectures for adders and subtractors.
- Utilizing micromagnetic simulation tools for performance evaluation.
- Comparison of the proposed APN designs with state-of-the-art approaches.
Main Results:
- A significant reduction of approximately 50%-80% in nanomagnet count and clock cycles compared to existing methods.
- Achieved area and energy efficiency without compromising computational accuracy.
- Demonstrated runtime reconfigurability in a single APN design layout.
Conclusions:
- The proposed APN architecture offers a highly efficient and scalable solution for implementing approximate arithmetic logic.
- This approach paves the way for developing more compact and power-efficient nanomagnetic computing systems.
- The demonstrated reconfigurability and performance improvements highlight the potential of APN designs in future computing paradigms.
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