Low-Power Hardware Implementation of a Support Vector Machine Training and Classification for Neural Seizure...

Area of Science:

• Biomedical Engineering
• Computer Engineering
• Machine Learning

Background:

• Epilepsy seizure detection requires efficient algorithms.
• Support Vector Machines (SVMs) are effective but computationally intensive.
• Hardware acceleration is crucial for real-time, low-power applications.

Purpose of the Study:

• To develop and implement a low-power hardware system for neural seizure detection.
• To accelerate Support Vector Machine (SVM) training and classification.
• To optimize the trade-off between sensitivity and power consumption.

Main Methods:

• Hardware implementation of Sequential Minimal Optimization (SMO) for SVM training.
• Integration of feature extraction and classification blocks.
• Deployment on Field Programmable Gate Array (FPGA) and Application-Specific Integrated Circuit (ASIC) platforms.

Main Results:

• Achieved a seizure detection sensitivity of approximately 96.77% with a linear kernel classifier.
• Demonstrated significant power consumption reduction, with ASIC consuming 2X less power than FPGA.
• Developed a hardware accelerator IP for efficient SVM training.

Conclusions:

• The proposed hardware-accelerated SVM system offers a highly sensitive and power-efficient solution for neural seizure detection.
• ASIC implementation provides superior power efficiency compared to FPGA.
• The system is suitable for real-time, low-power embedded applications.