Alignment tolerant, low voltage, 0.23 V.cm, push-pull silicon photonic switches based on a vertical pn junction

Area of Science:

• Photonics
• Semiconductor Devices
• Integrated Optics

Background:

• Silicon photonics offers a promising platform for optical communication and computation.
• Carrier depletion switches are crucial components for optical signal processing.
• Existing designs often face challenges in efficiency and fabrication compatibility.

Purpose of the Study:

• To design, fabricate, and characterize a novel carrier depletion silicon-photonic switch.
• To achieve high modulation efficiency and fast switching speeds.
• To ensure compatibility with standard complementary-metal-oxide semiconductor (CMOS) fabrication processes.

Main Methods:

• Utilized a highly doped vertical pn junction design.
• Employed a lumped configuration for fast switching.
• Characterized device performance including modulation efficiency and switching time.
• Assessed fabrication tolerance for commercial foundry integration.

Main Results:

• Achieved a high modulation efficiency of 0.23 V·cm.
• Demonstrated fast switching times as low as 60 ps.
• Fabrication process showed high tolerance to deviations.
• Seamless transfer to a 350 nm CMOS process node is feasible.

Conclusions:

• Successfully demonstrated a highly efficient carrier depletion silicon-photonic switch.
• The vertical pn junction design is key to achieving superior performance.
• The developed technology is suitable for mass production in commercial CMOS foundries.
• Medium resolution lithography is sufficient for fabricating these advanced devices.