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Improvement on Fully Filled Through Silicon Vias by Optimized Sputtering and Electroplating Conditions
1The 54th Research Institute of China Electronics Technology Group Corporation, Shijiazhuang 050081, China.
Materials (Basel, Switzerland)
|November 14, 2019
Summary
Optimizing sputtering and electroplating conditions significantly enhances the reliability of through-silicon vias (TSVs) for integrated circuit packaging. This improvement is attributed to the interface effects within the TSV structure, crucial for high-density applications.
Area of Science:
- Materials Science
- Electrical Engineering
- Semiconductor Manufacturing
Background:
- High-density integrated circuit packaging demands reliable through-silicon vias (TSVs).
- Electroplating is a key technology for fabricating fully filled TSVs.
- Optimizing fabrication processes is essential for enhancing TSV reliability.
Purpose of the Study:
- To improve the reliability of fully filled TSVs through process optimization.
- To investigate the impact of seed layer structures and fabrication parameters on TSV quality.
- To understand the interface effects influencing TSV performance.
Main Methods:
- Fabrication of TSV samples using varied sputtering and seed layer treatment approaches.
- Optimization of electroplating conditions and profile adjustments.
- Characterization of TSV quality using X-ray equipment and scanning electron microscopy (SEM).
Main Results:
- Optimized sputtering and electroplating conditions led to improved TSV quality.
- Different seed layer structures and fabrication methods showed varying effects on TSV integrity.
- Interface effects were identified as a critical factor in TSV reliability.
Conclusions:
- Optimized sputtering and electroplating processes are crucial for high-quality TSVs.
- Seed layer engineering and process control significantly impact TSV reliability.
- Understanding interface effects is key to advancing TSV technology for integrated circuits.
