Process Optimization of Via Plug Multilevel Interconnections in CMOS Logic Devices.

Area of Science:

• Materials Science
• Electrical Engineering
• Semiconductor Device Fabrication

Background:

• Multilevel metallization (MLM) is essential for modern CMOS logic devices.
• Via structures are critical components in MLM, enabling interconnections between metal layers.
• Optimizing via fabrication is key to improving device performance and reliability.

Purpose of the Study:

• To optimize the device and wiring in via structures for MLM in CMOS logic devices.
• To determine the most effective barrier deposition scheme for Tungsten (W) plug processes.
• To evaluate the impact of the optimized scheme on via resistance and reliability.

Main Methods:

• Investigated optimized barrier deposition schemes, including RF etching, Ion Metal Plasma Titanium (IMP Ti), and Chemical Vapor Deposition Titanium Nitride (CVD TiN).
• Characterized resistivities and bottom coverages of barrier layers at a 3.2:1 aspect ratio.
• Measured specific resistance of Tungsten film and via resistance under various conditions, including misalignment.

Main Results:

• The optimized barrier scheme (RF etching 200 Å, IMP Ti 200 Å, CVD TiN 2 × 50 Å) resulted in low resistivities (73 μΩ·cm for IMP Ti, 280 μΩ·cm for CVD TiN) and high bottom coverages (57% and 80%, respectively).
• Specific resistance of the Tungsten film was ~11.5 μΩ·cm, enabling smooth via filling.
• Via resistance was consistently below 20 Ω, even with side misalignment of 0.05 μm and line-end misalignment of ~0.1 μm.

Conclusions:

• The optimized barrier deposition scheme significantly enhances the Tungsten plug process for MLM via structures.
• The proposed scheme ensures low via resistance and high reliability, crucial for advanced CMOS logic devices.
• The findings provide a practical guideline for fabricating robust via structures in semiconductor manufacturing.