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Error metrics determination in functionally approximated circuits using SAT solvers.

Sa'ed Abed1, Ali A M R Behiry1, Imtiaz Ahmad1

  • 1Computer Engineering Department, College of Engineering and Petroleum, Kuwait University, Kuwait, Kuwait.

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This study introduces a novel SAT solver method for accurately measuring errors in approximate computing circuits. This approach speeds up error metric calculation and aids in debugging complex designs.

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Area of Science:

  • Computer Engineering
  • Digital Circuit Design
  • Formal Verification

Background:

  • Approximate computing offers accuracy-computation trade-offs by leveraging application error resilience.
  • Accurate error metric computation is crucial for evaluating approximate circuits.
  • Existing simulation-based methods face scalability and accuracy issues for complex designs.

Purpose of the Study:

  • To develop a fast and accurate methodology for determining error metrics in approximate circuits.
  • To address the limitations of simulation-based approaches for large-scale designs.
  • To enable precise evaluation of average-case and maximum error rates.

Main Methods:

  • Employing Boolean satisfiability (SAT) solvers for error metric determination.
  • Identifying all error-producing input assignments for comprehensive circuit quality assessment.
  • Developing a test generation method for design choices and debugging.

Main Results:

  • The SAT-based methodology accurately calculates maximum error rate and average-case error.
  • Achieved accurate error metric determination within acceptable CPU execution times.
  • Provided a log of error-generating input assignments for debugging purposes.

Conclusions:

  • The proposed SAT-based approach offers an efficient and accurate solution for evaluating approximate circuits.
  • This methodology facilitates better design choices and debugging of approximate computing hardware.
  • Enables reliable assessment of circuit quality for real-world applications.