FPGA-based hardware accelerator for SENSE (a parallel MR image reconstruction method).

Area of Science:

• Medical Imaging
• Computer Engineering
• Biomedical Engineering

Background:

• Parallel MRI (pMRI) techniques like SENSE accelerate data acquisition but face computational challenges with increasing receiver coils.
• Current FPGA accelerations for SENSE are limited to fixed parameters, hindering real-time applications.
• High computational demands of pMRI reconstruction limit real-time applications on general-purpose computers.

Purpose of the Study:

• To develop a flexible and high-performance FPGA-based hardware accelerator for the SENSE algorithm.
• To enable real-time, low-latency pMRI image reconstruction for various acceleration factors and coil numbers.
• To overcome the limitations of existing FPGA SENSE acceleration methods.

Main Methods:

• Designed and implemented a 32-bit floating-point FPGA hardware accelerator (HW-ACC-SENSE) using VIVADO High-Level-Synthesis.
• Integrated the HW-ACC-SENSE with an on-chip ARM processor for dynamic control of SENSE parameters (L and A_f).
• Tested the accelerator on in-vivo datasets using 8, 12, and 30 receiver coils, comparing performance against CPU implementations.

Main Results:

• The HW-ACC-SENSE demonstrated significant speed-up, achieving up to 298x faster reconstruction compared to single-thread and multi-thread CPU implementations.
• The proposed FPGA design maintained the reconstruction quality of the SENSE algorithm.
• The architecture supports flexible integration of multiple accelerator units for further performance enhancement.

Conclusions:

• The developed FPGA-based SENSE accelerator offers a substantial performance improvement for pMRI image reconstruction.
• This hardware acceleration enables real-time SENSE reconstructions with high flexibility for varying acquisition parameters.
• The HW-ACC-SENSE represents a significant advancement for accelerating pMRI techniques, addressing computational bottlenecks in clinical settings.