A high resolution time-to-digital-convertor based on a carry-chain and DSP48E1 adders in a 28-nm...

Area of Science:

• Digital Electronics
• Instrumentation and Measurement

Background:

• Accurate time measurement is crucial in various scientific and engineering fields.
• Existing time-to-digital-converters (TDCs) often face limitations in resolution, speed, or resource utilization.

Purpose of the Study:

• To develop a novel TDC architecture utilizing FPGA internal resources for high-resolution time tagging.
• To achieve picosecond-level time measurement resolution with improved efficiency.

Main Methods:

• Implementation of a new TDC architecture on a Field-Programmable Gate Array (FPGA).
• Integration of carry-chain logic and DSP48E1 adders within the FPGA for time measurement.
• Utilizing multiple TDC channels to enhance single-shot precision.

Main Results:

• A single TDC channel achieved an averaged bin size of 3.3 ps and 5.4 ps single-shot precision.
• Maximum sampling rate of 250 MSa/s with differential non-linearity of -3.3 ps/+24.1 ps.
• Four-channel configuration improved single-shot precision to 3.4 ps, demonstrating efficient resource usage.

Conclusions:

• The developed FPGA-based TDC architecture offers high time resolution (picosecond level) and efficiency.
• The design is suitable for multi-channel applications requiring precise measurement of multiple signals.
• This approach minimizes digital resource requirements for picosecond time measurement.