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Digital Circuit for Seamless Resampling ADC Output Streams.

Mauro D'Arco¹, Ettore Napoli¹, Efstratios Zacharelos¹

¹Department Electrical and Information Technologies Engineering (DIETI), University of Naples Federico II, via Claudio 21, 80125 Naples, Italy.

Sensors (Basel, Switzerland)

|March 19, 2020

Summary

Digital storage oscilloscopes (DSOs) lack fine sample rate control, necessitating offline processing. This study introduces a digital circuit for real-time, high-resolution sample rate adjustment within DSOs.

Keywords:

ASIC FPGA digital circuit design interpolating polynomial polyphase filter resampling

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Area of Science:

Electrical Engineering
Digital Signal Processing
Instrumentation

Background:

Digital storage oscilloscopes (DSOs) typically offer limited control over sample rates, requiring users to perform offline processing for fine adjustments.
This limitation hinders real-time analysis and efficient data acquisition.

Purpose of the Study:

To address the lack of fine resolution sample rate selection in DSOs.
To propose and evaluate a novel digital circuit for dynamic sample rate adjustment during data acquisition.

Main Methods:

The study reviews digital signal processing (DSP) techniques for digital resampling.
A new digital circuit is proposed, integrating between the analog-to-digital converter (ADC) and memory in DSOs.
The circuit employs a short digital filter with dynamic coefficients and a memory management strategy.

Main Results:

The proposed circuit enables selection of any sampling rate below the maximum with fine resolution.
The output sample rate can be asynchronous to the memory clock frequency.
Both Field Programmable Gate Array (FPGA) and Application-Specific Integrated Circuit (ASIC) implementations were assessed.

Conclusions:

The developed digital circuit significantly enhances the flexibility of DSOs by allowing real-time, fine-resolution sample rate control.
This innovation reduces the need for post-acquisition processing, streamlining waveform analysis.