Bottom-Gate Approach for All Basic Logic Gates Implementation by a Single-Type IGZO-Based MOS Transistor with Reduced...

Area of Science:

• Semiconductor device physics
• Integrated circuit design
• Nanoelectronics

Background:

• Complementary metal-oxide-semiconductor (CMOS) technology dominates electronic circuits but faces scaling limitations.
• Physical limits in transistor processing hinder further miniaturization of integrated circuits.
• A need exists for novel electronic concepts to overcome current technological barriers.

Purpose of the Study:

• To introduce a single-type channel multigate MOS transistor (SMG-MOS) as a next-generation electronic component.
• To demonstrate the processing adaptability and low static dissipation of SMG-MOS.
• To showcase the area reduction and design flexibility offered by SMG-MOS technology.

Main Methods:

• Development and theoretical analysis of the single-type channel multigate MOS transistor (SMG-MOS).
• Implementation of logic gates (NAND, NOT, AND, NOR, OR) using a single SMG-MOS transistor.
• Experimental validation and simulation-based analysis of SMG-MOS functional examples.

Main Results:

• SMG-MOS transistors can realize complex logic gates, typically requiring multiple CMOS transistors, within a single device.
• The SMG-MOS approach reduces the physical footprint of logic functions by up to 60% compared to CMOS.
• Simulations and experiments confirm the functionality and potential of SMG-MOS.

Conclusions:

• SMG-MOS technology presents a viable solution for scaling down complex integrated circuits.
• This approach enhances design flexibility and facilitates increased production rates.
• SMG-MOS represents a promising advancement for future electronic designs beyond CMOS limitations.