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Cryptographically Secure Pseudo-Random Number Generator IP-Core Based on SHA2 Algorithm.

Luca Baldanzi1, Luca Crocetti1, Francesco Falaschi1

  • 1Department of Information Engineering, University of Pisa, Via G. Caruso n. 16, 56122 Pisa, Italy.

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This study introduces a hardware accelerator for generating cryptographically secure random numbers, crucial for vehicle security systems. The validated design ensures robust encryption key generation, enhancing overall system safety.

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ASIC standard-cellFPGAHW acceleratorSHA2autonomous drivingcyber securityintelligent sensorson-chip random number generator (RNG)

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Area of Science:

  • Computer Engineering
  • Cybersecurity
  • Embedded Systems

Background:

  • Vehicle safety systems rely on secure data exchange.
  • Robust random number generation is vital for cryptographic key security.
  • Weaknesses in random number generation can compromise encryption.

Purpose of the Study:

  • To present a high-performance Cryptographically Secure Pseudo-Random Number Generator (CSPRNG) IP-core.
  • To develop a hardware accelerator for secure random number generation in automotive applications.
  • To enhance the security of vehicle sub-system communications.

Main Methods:

  • Developed a CSPRNG IP-core based on literature and standards.
  • Implemented architectural optimizations for timing performance and throughput.
  • Validated the IP-core using the NIST Statistical Test Suite.
  • Characterized the IP-core on FPGA and ASIC technologies.

Main Results:

  • Achieved high performance and throughput for random number generation.
  • Validated the randomness of generated numbers using NIST tests.
  • Demonstrated the IP-core's suitability for FPGA and ASIC implementation.

Conclusions:

  • The proposed CSPRNG IP-core provides a secure and efficient solution for automotive applications.
  • The hardware accelerator enhances the robustness of encryption key generation.
  • The design meets the stringent requirements for advanced vehicle safety systems.