A Learning Framework for n-Bit Quantized Neural Networks Toward FPGAs.

Area of Science:

• Computer Science
• Artificial Intelligence
• Hardware Acceleration

Background:

• Quantized Neural Networks (QNNs) are crucial for efficient AI model compression.
• Field-Programmable Gate Arrays (FPGAs) offer a flexible platform for deploying QNNs.
• Existing QNNs face challenges with gradient vanishing and hardware implementation efficiency.

Purpose of the Study:

• To propose a novel learning framework for n-bit QNNs with power-of-two constrained weights.
• To address the gradient vanishing problem in QNNs using a reconstructed gradient function.
• To develop an efficient QNN structure (n-BQ-NN) and hardware accelerator (SVPE) for FPGAs.

Main Methods:

• Developed a reconstructed gradient function for QNN back-propagation.
• Proposed a novel n-BQ-NN structure utilizing shift operations instead of multiplications.
• Designed a Shift Vector Processing Element (SVPE) array for efficient convolution on FPGAs.

Main Results:

• Quantized ResNet, DenseNet, and AlexNet models achieved accuracies comparable to full-precision models.
• The n-BQ-NN trained from scratch achieved state-of-the-art results against other low-precision QNNs.
• The n-BQ-NN with SVPE demonstrated 2.9x faster inference and reduced energy consumption by 31.3% compared to VPE on FPGAs.

Conclusions:

• The proposed learning framework effectively trains QNNs with power-of-two weights, maintaining high accuracy.
• The n-BQ-NN structure and SVPE array provide significant performance and energy efficiency improvements for FPGA-based inference.
• This approach offers a practical solution for deploying efficient and accurate deep learning models on resource-constrained hardware.