Efficient Acceleration of Stencil Applications through In-Memory Computing.

Area of Science:

• Computer Architecture
• Emerging Technologies
• Scientific Computing

Background:

• Traditional computer architectures face scalability limitations due to the memory bottleneck, exacerbated by big data and AI.
• Data-centric computing principles are emerging to address these limitations by moving computation closer to memory.
• In-memory and near-memory processing paradigms aim to reduce data transfer latency.

Purpose of the Study:

• To propose and evaluate in-memory associative processor architectures for stencil codes.
• To demonstrate the effectiveness of associative processors in alleviating the memory bottleneck for data-intensive scientific applications.
• To explore the implementation of these architectures using both memristor and SRAM technologies.

Main Methods:

• Developed two in-memory associative processor architectures specifically designed for 2D stencil computations.
• Implemented and simulated these architectures using both emerging memristor technology and traditional Static Random-Access Memory (SRAM).
• Evaluated the performance and efficiency of the proposed architectures across various stencil applications.

Main Results:

• The proposed in-memory associative processor architectures demonstrated promising efficiency for stencil code execution.
• Integration of processing and memory within associative processors effectively mitigates the traditional memory bottleneck.
• Both memristor and SRAM implementations showed viability for the proposed architectures.

Conclusions:

• Associative processors offer a viable and efficient solution for in-memory computation, particularly for stencil codes.
• The proposed architectures are well-suited for scientific stencil computing, addressing critical performance bottlenecks.
• Emerging technologies like memristors, alongside traditional SRAM, can be leveraged for future data-centric computer designs.